Jobs at Tenstorrent Inc.

Lead as a hybrid Chief of Staff and execution-focused TPM for the RISC-V software org: define goals, plan and track execution, manage dependencies and risks, drive cross-functional initiatives, support headcount and recruiting, prepare leadership materials, and represent the team to partners and customers.

Contract recruiter responsible for full-cycle hiring for supply chain, procurement, manufacturing operations, logistics, supplier quality, planning, and business operations. Build talent pipelines beyond LinkedIn, partner with hiring managers to scope roles and move searches, assess and close candidates, and maintain process-oriented, scalable recruiting workflows. 6-month contract, remote with location preferences.

Define and own chiplet-based compute platform architectures for high-performance RISC-V CPUs in SiP solutions. Lead design of PCIe, die-to-die connectivity, coherent fabrics, system management, and confidential computing subsystems. Collaborate with architecture, hardware, software, and external IP partners to deliver production-ready chiplet architectures and drive cross-functional execution.

Design board-level routing studies, mock-ups, and SI/PI modeling to support early-stage semiconductor package and package-board co-design. Collaborate with signal integrity, power integrity, mechanical, and system teams to develop PCB routing environments for BGA optimization, package escape studies, and system-level electrical modeling. Apply engineering judgment to evaluate tradeoffs and improve workflows using automation and data analytics.

Design and specify next-generation CPU networking for datacenter and automotive/robotics targets. Work at the intersection of NoC, performance modeling, and RTL to guide architecture, collaborate with hardware, software, and systems teams, and contribute to datacenter networking and early-stage automotive/robotics networking scoping and specifications.

The CPU Core Unit Lead will develop next-generation CPU RTL, define microarchitecture specifications, oversee design quality, mentor junior engineers, and use AI tools to enhance design processes.

Design and deliver die-to-die chiplet PHY IP in advanced FinFET nodes: develop PLLs and AMS blocks, lead design verification and layout interactions, support tape-out and silicon bring-up, and collaborate across architecture, digital, verification, layout, and software teams to achieve production-quality silicon.

Define architecture and micro-architecture specs for memory and I/O chiplets, evaluate next-generation memory technologies, develop performance and power modeling infrastructure, and collaborate with SoC, verification, physical design, packaging, systems teams and external partners to enable high-throughput, low-latency memory architectures.

Lead hardware-software co-design to enable AI/HPC and agentic AI stacks on RISC-V CPUs. Integrate and optimize low-level kernel infrastructure, runtimes, distributed execution, memory systems, and developer tools, collaborating with architects, compiler engineers, and kernel developers to meet performance targets.

Lead and enhance global People Operations, focusing on employee lifecycle management, operational excellence, and compliance across multiple regions.

As a Chip Design Lead at Tenstorrent, you will oversee the development of SoC programs from architecture to deployment, ensuring collaboration across teams and managing chip lifecycle processes.

Design and implement chip-level DFT strategies for high-speed CPU cores and multi-chiplet SiP. Implement and verify scan chains, memory BIST, and JTAG. Partner with RTL, physical design, and verification teams. Script and automate DFT flows using EDA tools (ATPG, fault coverage) and support SoC-level silicon debug, formal verification, and DFT signoff.

Own the flagship data-center AI compute product line: define topology, cabling, power, and orchestration; coordinate engineering, manufacturing, CX and sales; ensure reliable deployments in colos and customer data centers; support hardware, software, and firmware in the field; travel for installs and customer engagements; drive uptime, scaling, and total cost of ownership improvements.

Own and drive end-to-end product certification and regulatory compliance to enable customer shipments and revenue. Coordinate Sales, Systems Engineering, Operations, Manufacturing, and external agencies; remove roadblocks, manage escalations, track timelines and risks, and ensure products meet global import/export and regional regulatory requirements.

Lead and grow a software engineering team focused on RISC-V software ecosystem, collaborating with teams to establish RISC-V as the standard.

The Performance Architect will work on high-performance systems with expertise in software and hardware, focusing on AI and HPC solutions.

As a Senior Chiplet Physical Design Engineer, you'll design and integrate chiplets into a System-in-Package, focusing on synthesis and place-and-route, while collaborating with global teams.