The Senior Verification Engineer will verify SoC designs, develop UVM-based environments, create test plans, and debug issues in collaboration with design teams.
We’re looking for a Senior Verification Engineer to play a key role in verifying complex SoC and subsystem designs. You’ll work hands-on with design and architecture teams to ensure functionality, quality, and coverage goals are met across multiple projects.
Responsibilities
- Analyze architectural specifications and define verification requirements.
- Develop and maintain UVM-based verification environments.
- Create detailed test plans and develop corresponding test cases.
- Debug functional issues and contribute to root-cause analysis.
- Collaborate closely with design and architecture teams to align milestones and quality metrics.
Qualifications
- Bachelor’s or Master’s degree in EE, CS, or a related field.
- 7–10+ years of experience in verification or similar roles.
- Strong SystemVerilog and UVM expertise.
- Familiarity with Linux and standard EDA tools.
- Thorough understanding of the pre-silicon design and verification flow.
- Excellent communication, documentation, and teamwork skills.
Preferred / Plus
- Proven experience with coverage closure.
- Background in debugging complex designs.
- Strong analytical and problem-solving mindset.
Top Skills
Eda Tools
Linux
Systemverilog
Uvm
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