Design, implement, and verify RTL (Verilog/SystemVerilog) for ultra-low-latency FPGA trading systems. Build simulation testbenches and verification environments, run synthesis/place-and-route/static timing analysis, support hardware bring-up and debugging, and collaborate with senior engineers to meet strict latency and timing requirements.
About us
Edgehog Trading is a proprietary trading firm specializing in electronic options market making. We take a technology-driven approach, designing and operating automated, scalable systems to provide liquidity across markets.
Our team spans trading, engineering, and business operations, working together to build and support the systems that power the firm. We emphasize data-driven decision making, rigorous problem solving, and continuous improvement to navigate complex and evolving markets.
We operate in a highly collaborative environment where ideas can move quickly from concept to implementation, and where individuals are empowered to take ownership and contribute directly to the firm’s growth.
What you'll do:
- Design, implement, and verify RTL logic in Verilog or SystemVerilog targeting ultra-low-latency trading applications
- Develop simulation testbenches and functional verification environments to validate FPGA designs before hardware deployment
- Work closely with senior FPGA engineers and the trading infrastructure team to understand latency requirements and translate them into hardware design decisions
- Run synthesis, place-and-route, and static timing analysis; iterate on designs to meet strict timing constraints
- Participate in hardware bring-up and on-board debugging, using waveform analysis and other diagnostic tools
- Use AI tools to accelerate your development workflow — RTL review, testbench generation, debugging, and documentation
- Grow your understanding of market data protocols (Ethernet, PCIe, exchange feed formats) as they relate to the systems you build
Qualifications and skills:
- BS or MS in Electrical Engineering, Computer Engineering, or a related field
- Hands-on experience with RTL design in Verilog or SystemVerilog — coursework, personal projects, or internship experience all count
- Familiarity with FPGA simulation tools (e.g., ModelSim, QuestaSim, Vivado, Quartus) and the synthesis-to-deployment flow
- Understanding of digital logic fundamentals: state machines, FIFOs, clock domain crossing, timing constraints
- Comfort working in a Linux environment; Python, basic C or C++ is a plus
- Ability and eagerness to incorporate AI tools into your development and debugging workflow
- A strong desire to learn the HFT domain — no prior finance knowledge required
- Strong analytical instincts: when something behaves unexpectedly in hardware, you dig until you find it
Why Edgehog:
- Small team advantage: Direct access to founders and senior team members from day one
- Ownership early: Manage real P&L and make meaningful impact within your first year
- Cutting-edge tech: Work with our proprietary models and low-latency trading systems built in-house
- Tight feedback loops: Weekly 1-on-1s with your mentor, quarterly reviews with leadership
- Chicago-based: Affordable cost of living, vibrant trading community
Benefits:
- Comprehensive health, dental, and vision insurance with premiums 100% covered by the firm
- 401(k) with a 4% company match
- Unlimited paid time off and sick leave
- Free lunch, coffee, drinks, and snacks
- Commuter benefits
- Monthly happy hours and annual team events
The base salary range for this position is listed below. Base salary represents just one part of overall compensation; all full-time, permanent roles are eligible for a discretionary bonus and benefits, including items in the above list.
The base salary for this role is 100,000 - 175,000 USD per year
Edgehog Trading Chicago, Illinois, USA Office
363 W Erie St, Chicago, Illinois, United States, 60654
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