Top Remote Hardware Engineer Jobs in Chicago, IL

The Senior ASIC Physical Design Engineer will oversee the full physical design flow for complex SoCs, ensuring timing closure and optimization while collaborating with various teams and external providers on satellite projects.

Responsible for evaluating and developing new compute technologies, creating solutions for customer engagements, and maintaining partnerships within the compute domain.

Entry Level Diesel Technicians will perform preventative maintenance and minor repairs on diesel vehicles, using company tools and technology. Potential candidates should have basic mechanical skills, problem-solving ability, and strong communication skills, along with a valid driver's license.

As a Senior Hardware Engineer, you'll drive DPU integration into server platforms, execute validation testing, and develop automation for data analysis while collaborating with cross-functional teams and vendors.

The Physical Design Flow Engineer will develop methodologies for high-performance, low-power designs, focusing on PPA improvements and collaboration across various teams.

The Senior Engineer will develop AI-driven hardware models, assess SystemC simulation efficiency, and integrate modeling with EDA tools.

The role involves evaluating techniques for fault-tolerant quantum computing, assessing hardware performance, and conducting documentation and reporting for DARPA's QBI team.

Lead PCB/FPC design for consumer electronics: component placement, routing, signal and power integrity analysis, DFM, and producing fabrication/assembly packages. Manage vendors, release designs into PLM, author ECOs, and maintain ECAD libraries.

The Lead Mechanical Program Engineer coordinates complex engineering projects, ensuring adherence to Amazon's standards. They facilitate communication between teams, manage project schedules, and prepare risk assessments while promoting effective collaboration and strategic planning.

As an ASIC Design Verification Engineer, you will develop and execute verification strategies for AI inference ASICs, ensuring functional correctness and performance, while collaborating with design and architecture teams.