Get the job you really want.

Top FPGA Engineer Jobs in Chicago, IL

Reposted 18 Days AgoSaved
In-Office
Chicago, IL
125K-200K Annually
Mid level
125K-200K Annually
Mid level
Fintech • Software
The FPGA Engineer will design FPGA logic for trading, analyze results, and work on developing low-latency applications and timing closure.
Top Skills: PythonSystem VerilogVerilog
Reposted 2 Days AgoSaved
In-Office
Chicago, IL
200K-200K Annually
Junior
200K-200K Annually
Junior
Fintech • Quantitative Trading
As an FPGA Engineer, you will design and implement high-speed hardware for trading systems, collaborate with traders and developers, and advance low-latency techniques.
Top Skills: CC++SystemverilogVerilogVhdl
Reposted 5 Days AgoSaved
In-Office
Chicago, IL
225K-250K Annually
Senior level
225K-250K Annually
Senior level
Financial Services
The Senior FPGA Engineer will design, implement, and improve ultra-low-latency trading systems, collaborating with various teams to enhance performance and scalability.
Top Skills: C++FpgaPythonSystemverilogVhdl
Reposted 8 Days AgoSaved
In-Office
Chicago, IL
180K-280K Annually
Mid level
180K-280K Annually
Mid level
Financial Services
Join QRT as an FPGA Engineer, developing RTL for hardware platforms to accelerate high frequency trading. Work closely with trading teams to optimize solutions.
Top Skills: C/C++FpgaPythonRtl
Reposted 16 Days AgoSaved
In-Office
Chicago, IL
110K-160K Annually
Mid level
110K-160K Annually
Mid level
Fintech • Software • Financial Services • Quantitative Trading
Design and implement low-latency hardware-based trading solutions while collaborating with traders and engineers to analyze performance and resolve bottlenecks.
Top Skills: Fpga DesignSystemverilog
Reposted 9 Days AgoSaved
Remote
Chicago, IL
120K-150K Annually
Senior level
120K-150K Annually
Senior level
Aerospace • Defense
As a Senior FPGA Verification Engineer, you will architect and develop test benches, verify code functionality, and prepare design review materials.
Top Skills: CocotbPythonQuestasimRiviero-ProSystemverilogUvmVcsVerilatorVerilogVhdl
Reposted 21 Days AgoSaved
In-Office or Remote
Chicago, IL
Mid level
Mid level
Software
Design and implement CPLD and FPGA solutions for IP routing products, collaborating with other engineering teams and ensuring reliability and features align with requirements.
Top Skills: AlteraCpldFpgaI2CLatticePerlPythonSpiSvidSystem VerilogTclVerilogVhdlXilinx
5 Days AgoSaved
Remote
Chicago, IL
170K-195K Annually
Senior level
170K-195K Annually
Senior level
Aerospace • Manufacturing
The Lead RTL/FPGA Design Engineer will develop and manage high-performance coherent modems for free space optical communications, translating DSP algorithms into synthesizable RTL, ensuring compliance, and supporting integration and testing.
Top Skills: DspFpgaPerlPythonSystem VerilogTclVhdl
New

Track Smarter, Apply Better.

Ditch the spreadsheets. Organize your job search with our freeApplication Tracker.

Use For Free
Application Tracker Preview
All Filters
New Jobs
Job Category
Experience
Industry
Company Name
Company Size

Sign up now Access later

Create Free Account