Top FPGA Engineer Jobs in Chicago, IL

The FPGA Engineer will design FPGA logic for trading, analyze results, and work on developing low-latency applications and timing closure.

Design and implement low-latency FPGA-based trading solutions. Collaborate with traders, quantitative analysts, and low-level software engineers. Push FPGA performance, verify designs via simulation, resolve real-time system bottlenecks, and optimize SoC, memory, and high-speed transceiver subsystems.

As an FPGA Engineer at Belvedere Trading, you will develop high-performance FPGA systems, collaborate on trading algorithms, and optimize trading system performance.

Design, implement, and verify RTL (Verilog/SystemVerilog) for ultra-low-latency FPGA trading systems. Build simulation testbenches and verification environments, run synthesis/place-and-route/static timing analysis, support hardware bring-up and debugging, and collaborate with senior engineers to meet strict latency and timing requirements.

Join Optiver as a graduate FPGA engineer to design ultra-low-latency hardware and network interfaces for high-frequency trading. You'll develop FPGA/ASIC digital designs, research low-latency techniques, and collaborate with traders, software developers, and infrastructure engineers to integrate hardware with cutting-edge server platforms.

Work with a mentor to design and accelerate low-latency, high-speed FPGA hardware for trading systems. Tasks include hardware design, researching low-latency techniques, integrating FPGAs with server hardware, and collaborating with traders and software engineers on production-grade solutions.

Design, implement, optimize, verify, and debug complex FPGA solutions using RTL, simulation, and advanced testbenches. Collaborate on board-level interfaces, high-speed protocols, RF DSP, hardware integration, and system architecture. Document designs, support project milestones, improve development processes, interface with customers, and mentor junior engineers. Work cross-functionally with software, mechanical, hardware, and systems teams to deliver FPGA-based products.

As an FPGA Engineer, you will design and implement high-speed hardware for trading systems, collaborate with traders and developers, and advance low-latency techniques.

The Senior FPGA Engineer will design, implement, and improve ultra-low-latency trading systems, collaborating with various teams to enhance performance and scalability.

Design, implement, and test digital hardware and FPGA-based circuit cards across full product lifecycle. Work on high-speed interfaces, RF/EO DSP, embedded processors, prototype/debug subsystems, produce design/test documentation, and support production and fielded systems in an integrated engineering team.

The Senior FPGA Engineer will architect ultra-low-latency FPGA trading systems, mentor a team, and collaborate closely with quantitative researchers and software developers.

Design, implement, verify, and optimize FPGA-based digital signal processing systems. Responsibilities include architecture, RTL coding (VHDL/Verilog), HLS, testbench development, simulation, synthesis, place-and-route, timing closure, and hardware debugging for high-speed interfaces and embedded SoC architectures.

Lead full life-cycle digital hardware development using modern FPGAs and high-speed interfaces. Design, prototype, debug, test, and integrate complex circuit cards and subsystems. Translate system specs to hardware/test requirements, work with cross-functional teams, and support production and fielding for defense-related sensing and EW systems.

Lead full lifecycle FPGA and digital hardware design for EW and sensor systems: system requirements, digital circuit design, FPGA implementation, prototyping, test/verification, production support, and cross-functional team leadership.

Own FPGA prototyping and silicon bring-up for next-generation communications ASICs. Build FPGA-based platforms, support first-silicon debug, validate high-speed interfaces, develop automated test infrastructure, and collaborate across ASIC, firmware, software, and systems teams.

Implement and optimize RF DSP algorithms in HDL for real-time FPGA execution, prototype algorithms in Python and port to ARM SoCs, collaborate on instrument bring-up, calibration and system integration with RF hardware teams, author design documentation and test reports, and work in a hybrid Mountain View office.

The Lead RTL/FPGA Design Engineer will develop and manage high-performance coherent modems for free space optical communications, translating DSP algorithms into synthesizable RTL, ensuring compliance, and supporting integration and testing.