Own Niobium Microsystems’ developer relations function by helping developers use Fully Homomorphic Encryption, creating technical examples and documentation, building open-source and developer communities, improving onboarding and adoption, presenting at technical events, and translating complex concepts into accessible content. The role requires strong C++ or Python programming, developer-facing experience, familiarity with GitHub and Discord, and the ability to work independently in an evolving startup environment.

The Senior Design Verification Engineer will verify complex SoC and RTL designs using SystemVerilog and UVM. Responsibilities include developing test plans, testbenches, tests, and coverage metrics; running simulations; analyzing failures; debugging RTL; documenting verification results; and collaborating with internal teams, vendors, and contractors. The role also leads technical projects and mentors junior engineers. Experience with gate-level simulation, Cadence verification tools, ASIC flows, and programming languages is required.

Lead end-to-end ASIC physical design for complex SoCs from RTL handoff through GDSII tapeout. Responsibilities include floorplanning, hierarchical integration, place and route, timing closure, CTS, PPA optimization, low-power implementation, IR/EM and physical verification sign-off, and collaboration with architecture, RTL, DFT, packaging, and SI teams. Mentor physical designers, establish methodologies and quality standards, manage schedules, and drive multiple advanced-node tapeouts.